The present invention relates to a computer system which utilizes a multi-way set-associative cache memory, the multi-way set-associative cache memory providing fast multiple-word accesses.
Most modern computer systems include a central processing unit (CPU) and a main memory. The speed at which the CPU can decode and execute instructions and operands depends upon the rate at which the instructions and operands can be transferred from main memory to the CPU. In an attempt to reduce the time required for the CPU to obtain instructions and operands from main memory, many computer systems include a cache memory between the CPU and main memory.
A cache memory is a small, high-speed buffer memory which is used to hold temporarily those portions of the contents of main memory which it is believed will be used in the near future by the CPU. The main purpose of a cache is to shorten the time necessary to perform memory accesses, either for data or instruction fetch. The information located in cache memory may be accessed in much less time than information located in main memory. Thus, a CPU with a cache memory needs to spend far less time waiting for instructions and operands to be fetched and/or stored.
A cache memory is made up of many blocks (also called lines) of one or more words of data. Each block has associated with it an address tag that uniquely identifies which block of main memory it is a copy of. Each time the processor makes a memory reference, an address tag comparison is made to see if a copy of the requested data resides in the cache. If the desired memory block is not in the cache, the block is retrieved from the main memory, stored in the cache and supplied to the processor.
In addition to using a cache to retrieve data from main memory, the CPU may also write data into the cache instead of directly to the main memory. When the processor desires to write data to the memory, the cache makes an address tag comparison to see if the data block into which data is to be written resides in the cache. If the data block exists in the cache, the data is written into the data block in the cache and a data "dirty bit" for the data block is set. The dirty bit indicates that data in the data block has been modified, and thus before the data block is deleted from the cache the modified data must be written back into main memory. If the data block into which data is to be written does not exist in the cache, the data block must be fetched into the cache or the data written directly into the main memory.
In a multi-way set-associative cache a single index is used to simultaneously access a plurality of data random access memories (RAMs). A data RAM may be implemented by one or more physical random access memory integrated circuits. A set is a collection of all lines addressed by a single cache index. The number of data RAMs addressed by a single cache index indicates the way number of a cache. For example, if in a cache a single cache index is used to access data from two data RAMs, the cache is a two-way set-associative cache. Similarly, if in a cache a single cache index is used to access data from four data RAMs, the cache is a four-way set-associative cache.
When a multi-way access is made, a tag comparison is made for each data RAM. If a tag comparison indicates the desired data block is in a particular data RAM the operation is performed on/with data from that particular data RAM.
Typically, a cache allows the access of one word at a time. Many systems, however, implement functions performed on multiple-words, for example in floating point arithmetic functions. In order to access, for example, a two-word value it is necessary to make two cache memory accesses in a typical cache. In order to allow for a single cache memory cycle access of a two-word value, some prior art systems have doubled the output size and hence the number of random access integrated circuits used in the implementation. This, however, significantly increases the hardware cost of the cache memory.